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DspEdu 2.1 1. Current Waveforms in the Plant Electrical Distribution System with UPS Load 2. Triple-n Harmonics Due to UPS Load 3. Single Phase Boost Type PWM Rectifier 3.2 Current Control Strategies 3.2.1 Controlled ON time Zero Current Switching Technique 3.2.2 Peak Current Sensing – Zero Current Switching Technique 3.2.3 Hysterisis Current Control |
Suresh
Kumar. K.S.
Department of Electrical Engineering National Institute of Technology Calicut Calicut-673601, Kerala State , India [ This article was prepared for a 3-day short-term course I offered to working professionals from UPS Industry in 1998-2001 period.]
The front-end converter of on-line UPS converts a.c line to d.c inside and delivers power to the inverter of UPS and also for battery charging. This front-end can be of different types as explained below. (1) Single Phase Uncontrolled Rectifier with Capacitance Filter In this case the d.c side control i.e. battery charging control is exercised after the capacitor filter by means of a thyristor buck stage with smoothing inductor. The current drawn from the power line will be very much distorted and will be rich in third harmonic. Also the line power factor will be low. Hence this kind of front end is not advisable for units above 1kVA rating. However there are many UPS firms who use this front-end for even 5-10kVA range. (2) Single Phase Fully Controlled SCR Bridge with d.c side smoothing Inductor Here phase control of a fully controlled thyristor single phase bridge is employed to control the current in a d.c side choke which feeds the battery node. The harmonic performance tends to be much better than in the case of uncontrolled rectifier. However, being a single-phase system, the line current drawn will contain third harmonic even in this case. This converter is preferred in the 1-2kVA range. Above 2kVA level ,a three phase input front-end is preferable from triplen harmonic current and neutral overloading point of view. (3) Three-phase uncontrolled rectifier with capacitor filter Similar to (1), but three-phase input. The line current will be distorted. But it will not contain third harmonic or any other triplen harmonic. Also, the neutral current will be zero. In fact there is no neutral connection anywhere in a six-pulse diode rectifier. (4) Three-phase fully controlled SCR Converter with d.c side Inductor Similar to (2), but three-phase input. The line current distortion will be the least in this case. This front-end is preferable from 2kVA UPS rating onwards. In order to clarify various aspects of impact of UPS loads on the distribution system a comparative study of various types of UPS front-ends is carried out here.15kVA UPS load is to be supplied from a DB which receives supply via a 35 sq.mm 31/2 core cable of 100m length from the main switch board. The UPSs are located 25m from the DB. Three cases are considered here. Case 1 – Three no. Single Phase Input 5kVA UPS units with uncontrolled rectifier type front-end connected to R, Y and B phases at the DB using three 2 core cables of 6sq.mm size and 25m length. Case 2 – A three-phase uncontrolled rectifier type front-end UPS of 15kVA rating connected through 25m of 6 sq.mm 3 core cable. Case 3 - A three-phase uncontrolled rectifier with d.c side choke type front-end UPS of 15kVA rating connected through 25m of 6 sq.mm 3 core cable. In all the cases the UPSs were assumed to deliver rated kVA at 0.8p.f at their outputs and their inverter efficiency was taken as 90%.The behaviour of the front end converters for the three cases were simulated using Pspice Simulation package and the line current and neutral current waveforms in the 3 ½ core 35 sq.mm cable supplying the DB are shown in Fig.1.Also note that the return conductor current in the three single phase cables supplying the individual UPS units will be the same as the line current.
Fig.1 Line and Neutral Currents in the Feeder supplying three 5kVA Single Phase UPS units. The r.m.s line current is 34.2A and r.m.s neutral current is 59.2A.The line current is rich in harmonics and has a THD of 128%.Its third harmonic content is 90%.The triplen harmonic currents drawn by the three single-phase UPSs add in the neutral to yield a high level of neutral current in the three-phase cable-neutral current is as much as double the phase current! The total power taken is 14.3kW and the apparent power is 23.6kVA-thus the power factor is ~0.6. A 6 sq.mm cable has a current carrying capacity of about 35Amps.Here the r.m.s current is 34.2 Amps and hence the cables supplying the single phase UPS units appear to be fully loaded. But the current flowing in these cables have a THD of 128% and with such a large THD of current the cable has to be considerably derated. The rating is likely to be around 20A at this THD level. Hence the cable is grossly overloaded. 6sq.mm is capable of handling 8kVA per conductor if the current is undistorted i.e 24kVA of three-phase power. But in the present context it is going to be overloaded. A 5 kVA load requires only a 32A Switch-Fuse unit. But not a 5kVA Single-phase UPS! Such a UPS takes around 8kVA of distorted power and it takes 34.2 Amp of r.m.s current. A 32 A SFU will burn out. In fact the actual current taken by such a 5kVA UPS at full load will be more than 34.2A due to various converter losses which were ignored in the simulation. A 35-sq.mm cable has a current carrying
capacity of 92Amps.In a 3 ½ core cable, the neutral conductor will
have 46Amps capacity. And in the present case the neutral in the cable
has to carry 59.2 Amperes of third harmonic current. In fact, due to increased
in conductor resistance at higher frequencies, the current rating of neutral
at 150Hz will be less than 46Amps.Thus there is going to be considerable
neutral overheating, burning and cable damage in this 100m,35 sq.mm cable
supplying three 5kVA single phase UPS units.35 sq.mm cable has 66kVA kVA
carrying capacity-but not if the neutral is harmonically loaded. In this
case we will require a 70sq.mm 3 ½ core cable to supply this UPS
load if neutral overheating in the cable is to be prevented.
Fig.2 Line Current Waveforms in the cable supplying a 15kVA Three-phase UPS Fig.2 above shows the current waveforms in the three lines supplying 15kVA three-phase UPS with uncontrolled rectifier/capacitor front-end and delivering 15kVA at 0.8 p.f at output. There is no neutral connection and no neutral current. Also, the triplen harmonic content in the line is zero. The r.m.s value of line current is 28.7A and its THD is 90%. The dominant harmonic is the fifth at 72%. The power drawn is 14.3kW and the apparent power drawn is 19.8kVA yielding a power factor of 0.72.Though the r.m.s value of current in the 6sq.mm 4 core cable is below its rated value of 35Amps, this cable is likely to be fully loaded at this loading condition due to the distorted nature of current. But in this case a 32A three-phase SFU will be sufficient unlike in the single-phase case. Also, there is no overloading of any kind on the 35 sq.mm 3 ½ core feeder. Fig.3 below shows the line currents
in the case of a 15kVA three phase UPS with uncontrolled rectifier plus
Choke-Capacitor Filter. The r.m.s value is 22Amps and the THD is 28.4%.
The power drawn is 14.3kW and apparent power drawn is 15.3kVA indicating
a power factor of 0.93.Both the cables are being operated well under their
rating
The table below gives the details of harmonic content of the line currents in the three cases.
The effect of distorted currents introduced by UPS units, especially the Single-phase input UPS units, into the Plant Electrical Distribution System can result in thoroughly distorted bus voltages and all the attendant problems. Especially so when the system is run on the standby DG Set. The Table below shows the internationally
accepted IEEE STD 519 Current Distortion Limits for Non-Linear Loads. These
limits have to be observed by every power consuming equipment taking more
than 50W or so in the European countries. Also, United States and other
North American countries have imposed similar restrictions on customers
who employ non-linear loads.
The typical context in which Small and Medium Power UPS units are connected the ratio Isc/IL will be below 50 and hence the total harmonic distortion permitted will be about 8.0%.This level of THD is unattainable in Thyristor based AC-DC Converters unless heavy passive filters are employed outside the UPS unit. The modern day power electronic technique of Active Power Factor Corrected Converter comes in at this point. This kind of AC-DC converters draw pure sinusoidal current at unity power factor from the a.c lines, at the same time maintaining the output d.c voltage constant against variations in d.c side load and a.c side line voltage variations. Though they are called power factor corrected converters they are actually harmonic corrected converters with unity power factor operation thrown in as a bonus. No statutory harmonic limits have been imposed by any of the SEBs in India till now. Hence selling UPS units that violate IEEE 519 limits on harmonic currents is not yet a violation statutes in our country. However, both the consumers and the utility authorities have become sharply aware of the havoc that excessive harmonic currents in Power systems can play with equipment and their operation. The imposition of harmonic limits and penalty clauses in Indian SEBs is only a matter of time. The growing awareness on the harmonic distortion front is best exemplified by the insistence of Department of Telecommunications on Active Power Factor Corrected Battery Chargers for their Telephone Exchanges. Many Exchanges have already switched over to what they call ‘SMPS Type Float Charger System’ which is essentially a three phase Active PFC a.c to d.c converter (comprising three independent single phase Active PFC units; one for each phase) followed by a d.c to d.c high frequency converter to translate the PFC output d.c voltage to 48V battery level and to control the d.c output current. The SMPS type Charger comes in modular form with each module capable of delivering 200Amps d.c current into a 50V d.c bus. Also, many reputed UPS manufacturers in India already offer Active PFC type front end as an option - an option which may well become mandatory in the near future 2. Triple-n Harmonics Due to UPS Load Single Phase and Three Phase controlled and uncontrolled rectifiers in UPS Systems form a major source of current harmonics in the power distribution system. Single Phase Rectifier input UPSs are usually of low capacity;however they are used in a large number and in a variety of equipment and hence pose a more serious harmonic threat at the 440V and 11kV power distribution system levels. In addition ,the current harmonics injected by them into the power distribution system is more detrimental due to the predominant triplen harmonic content in them. The figure below shows a Single Phase rectifier supplying an SMPS load and the supply line current drawn by it. This line current is dominated by third harmonic(to the extent of 130% usually) and results in noticeable sag at the peak of line volts.
Fig. 4 A conventional diode bridge feeding a SMPS load
Fig. 5 Waveforms of the Circuit A large number of such Single Phase Rectifier loads in a distribution system results in serious overloading of neutral conductor due to addition of triplen harmonic content in the neutral conductor. Triplen harmonic content drawn by all the uncontrolled rectifiers will be more or less in phase and hence possibility of cancellation due to phase difference does not exist. Thus, triplen harmonic content in neutral conductor will be sum of triplen harmonic content of all the uncontrolled rectifiers in the three phase of the distribution system (irrespective of whether the rectifier loads are balanced among the Three Phases or not). With stringent harmonic restrictions in the offing, on-line UPS systems will be required to comply with harmonic injection standards in future. This will result in a replacing of thyristor phase controlled converter by Boost type power factor corrector stage to ensure sinusoidal input current at unity power factor. This system is especially attractive at higher ratings. The boost type PFC can work directly from line generating current flow into a 360V battery node. The control is much simplified since the battery across the output of PFC will make a voltage control loop redundant. Simple current control loop with a battery current reference set based on the battery voltage will do. The inverter can run directly from the 360V bus and generate 230V output. An output transformer is optional and is needed only if isolation from mains is essential. Various passive correction schemes aimed at improving the power factor and THD(Total Harmonic Distortion) of Single Phase uncontrolled rectifiers at low power levels (typically less than 50W) are in use ;especially in electronic ballast for Fluorescent Lamps and CFLs. However, Active PFC is preferred at power levels above 50W.This lecture dwells on Active PFC using Boost Conversion technique in Single Phase context. The principles, control strategies,design considerations etc. will remain applicable for Three Phase systems too. However, all explanations will be with reference to Single Phase units for the sake simplicity. This article will deal with the most common Active PFC topology viz. Single Switch Boost Type PFC(SSB-PFC) . 3. Single Phase Boost Type PWM Rectifier A simplified schematic of a Single
Phase Boost Type PWM Rectifier is shown below. The a.c line is full wave
rectified using a conventional diode rectifier and the rectified output
is applied to the boost converter stage which is controlled to maintain
a constant DC Voltage across the output capacitor against variations in
dc side load and ac side voltage.
The Principle
Assume that by a suitable starting control strategy a DC side voltage Vo (which should be greater than the maximum of line i.e. Vm for proper operation of this converter) has been created. Now,if the switch Q is kept on ,the current in the inductor L increases from whatever it was at the instant of switch closure. Hence, it is possible to increase the current in L by closing the switch. And,if the switch Q is opened ,whatever current that was flowing in the inductor at the instant of opening the switch will force itself into Co through the diode D since current in an inductor can not be broken instantaneously in a system which is devoid of impulse voltages. But then ,if D conducts the voltage across L changes polarity(because Vo is assumed to be more than even Vm) and hence current in it decreases from its initial value. Thus, it is possible to increase the current in L by closing Q and to decrease the current in L by opening the switch Q. If it is possible to raise or lower the inductor current by controlling Q ,it follows that it must be possible to make the inductor current track a pre-specified wave shape by suitably controlling the switch on/off periods.Using this strategy, the current in L in this converter is made to follow a Full Wave Rectified wave shape. If the current in L is full wave rectified in shape, the line current in the a.c side will be pure sinusoidal and in phase with supply voltage due to the modulation process involved in the bridge rectifier. This is the principle of operation of boost type single phase PFC circuit. The ideal control requirements of the PFC circuit under steady state are (i) maintain a pure D.C. output voltage of constant value and (ii) maintain input current wave shape as pure sinusoidal at u.p.f i.e. essentially emulate a resistor in the a.c side. Under steady state the D.C. side load removes energy from capacitor at constant average rate and the capacitor voltage can be maintained constant only if the incoming power from the diode side is equal in value to the outgoing power in the average. The D.C. side load need not be linear always and the incoming power is anyway not constant on an instant to instant basis. Hence, even if the average powers are equal the instantaneous values are not and the mismatch will flow into the capacitor thereby producing a.c ripple across it. Use of a large valued capacitor will reduce this ripple to acceptable level. It is the voltage control loop , which ensures that the input power from the a.c side is equal to the output power demand plus losses at the specified output voltage. This loop senses the output voltage,increases the current drawn from the line if output voltage tends to decrease from the set value and decreases the current drawn from a.c side when output voltage tends to increase. But the voltage control loop can not ask the PFC circuit to draw the required power at an arbitrary current wave shape. The wave shape of line current should be pure sine at u.p.f or equivalently the current in inductor L has to be pure full wave rectified shape. Hence, only the amplitude of this full wave rectified shape is the free variable to be decided by the voltage control loop. There has to be another control loop to see that the inductor current has the desired wave shape and the amplitude as commanded by the voltage control loop. The current control loop fulfils these functions. Thus there are two control loops – the outer voltage control loop which monitors output voltage and decides the amplitude of full wave rectified current that should flow in the boost inductor and the inner current control loop which monitors the boost inductor current and forces it to track the desired wave shape with an amplitude decided by the outer loop. 3.2 Current Control Strategies Different control strategies exist for the control of wave shape of boost inductor current. They can be broadly classified into discontinuous conduction methods and continuous conduction methods. In discontinuous conduction strategies, the inductor current ramps down to zero every time the switch is kept off. It is switched on again only after inductor current touches zero or remains at zero for some time. In the continuous conduction methods, the inductor current remains above zero always. Two popular discontinuous methods and two continuous methods are detailed below. 3.2.1
Controlled ON time Zero Current Switching Technique
In this scheme, the voltage control loop controls the ON period of the switch direcly. The voltage control loop senses the output voltage,compares it with the set reference level,forms the processed error signal and converts this error signal into a proportional pulse width. The width of this pulse decides the ON time of the boost switch in a switching period and will remain constant under steady state. During the OFF period of the switch the inductor current ramps down and is allowed to go to zero. The current zero is sensed (using a current sense resistor) and the switch is switched ON when the current touches zero. Thus in every switch cycle the inductor starts at zero current ,ramps up linearly to a peak value proportional to the value of a.c voltage at that time(since ON period is kept constant in all switch cycles),and then ramps down to zero linearly. Hence over a switching period the inductor current will be a triangle with a peak value proportional to the a.c voltage value. The average current in L during one switching period is the average of this triangle and is equal to half the peak value ,and hence, is proportional to a.c voltage value. Thus, the inductor current average will have sinusoidal shape. Strictly speaking , there is no current control loop in this scheme and control of current wave shape is implicitly done. The inductor current waveform and the switch control signal are illustrated in the figure above. The advantages of this scheme are simplicity of control,absence of diode reverse recovery related problems etc. But the peak switch current and diode current will be twice the required line current and will be excessive at low line voltage conditions. This increases the current stresses in the Switch(usually MOSFETs or IGBTs) and diodes. The switching ripple content in the inductor current is almost as large as the required average current and this calls for large filter components in the line side to smooth the line current and for RFI filtering. These considerations limit the applicability of this strategy to low power applications –typically under 300W. The Power Factor Controller IC UC 3852 ,brought out by Unitrode Corporation, is tailor made to implement this control strategy. This IC also permits implementation of feed forward control of switch ON time to achieve fast control against line voltage variations. 3.2.2 Peak Current Sensing – Zero Current Switching Technique This technique is similar to the technique described above and is a discontinuous current control scheme. The above scheme suffers from inaccuracies in the waveform shape control due to host of factors like quality of inductor winding ,switching times of switch and diode and their variation with load and voltage ,errors in voltage to pulse width conversion etc. 'Peak Current Sensing – Zero Current Switching' technique results in better control of current wave shape and results in lower THD. The two control loops-voltage control loop and current control loop – are explicitly present in this scheme. The voltage control loop monitors the output voltage and outputs the reference current, which should flow in the boost inductor. This current will have the full wave rectified shape and an amplitude suitable for meeting the power balance requirement and it becomes the input into the current control loop. The current control loop keeps the Switch ON until the Switch Current reaches a level equal to twice reference current at that instant. At that point Switch is opened and inductor current is allowed to ramp down to zero. The zero current condition is sensed and the Switch is allowed to go ON at that instant. Hence the average inductor current in a switching cycle follows the reference current waveform (which is full wave rectified in shape).In fact the inductor current wave shape and switch control signal will be identical for both the above schemes if all the components are ideal. The zero current sensing can be done either by resistive current sensing in the inductor path or by sensing the sudden change in polarity of inductor voltage when the diode stops conducting. This is done by a secondary winding of suitable turns in the inductor. This method is preferred since another current sensing (switch current )is already involved for detecting the peak current condition. The switch current is sensed either by a resistor in series with the switch or by a current transformer in the switch line. Both the current control schemes suffer from (i) high peak currents in the devices (ii) excessive switching ripple making ripple and RFI filtering more difficult (iii) excessive EMI levels due to large range current changes involved and (iv) switching frequency which varies with line voltage waveform and magnitude and with load. The variable switching frequency makes it still more difficult to design suitable RFI filters. Peak Current Sensing – Zero Current Switching method has been made popular by a tailor made power factor controller IC from Motorola – MC34262.(Price ~ RS100/-).This IC makes it very easy to implement this control strategy with a few external components. It employs resistive Switch current sensing and secondary winding on boost inductor for current zero sensing. The D.C. supply needed for the IC is also derived from the secondary winding. The IC also offers some protection features. This control strategy, implemented with the help of MC34262, will be the most economical choice for the power range 50W-500W.Above 500W it becomes difficult to maintain good efficiency ,esp. at low input voltage levels. And RFI filtering becomes very difficult. 3.2.3 Hysterisis Current Control This is a continuous current ,variable switching frequency current control scheme. The boost inductor current is continuously compared with the reference current waveform ( which is obtained from the voltage control loop ) and the error signal after amplification is fed into a Hysterisis Comparator. When the actual inductor current goes above the reference current by the comparator hysterisis band the comparator changes state. This state change is used to switch off the boost switch and the current ramps down. When the inductor current goes below the reference current by camparator hysterisis band it changes state again and this state change is used to turn the boost switch on. Thus, the inductor current is always maintained within ± D V where 2 D V is the total hysterisis band. The ripple content in the inductor current can be reduced by decreasing the hysterisis band and that will result in higher switching frequency. The switching frequency varies as function of instantaneous value of input voltage and also with the D.C. side load. The ripple content in the inductor current is not time-position dependent since the hysterisis band is constant. This results in a very high attenuation requirement in the ripple filter in the line side to avoid distortion near zero crossing of current waveform. Also, the ripple content in the inductor current is independent of load and hence filtering requirements will be stringent at low load conditions. Ripple filtering is made more difficult by the varying nature of the switching frequency. This is the most important disadvantage of this scheme. Variable hysterisis band,error triangularisation etc are techniques that have been proposed to overcome the switching frequency variation in the hysterisis control scheme. However incorporating such techniques will offset the advantage obtained by opting for hysterisis control – i.e. simplicity of control is compromised. The figures below show the simulated line current waveforms and switch control waveforms for a 1kW PFC employing hysterisis current control ,working from 230V supply ,at two load levels. The RFI Filter was removed in the simulation to show the hysterisis action in the current. It may be seen that at full load the averaged line current is a close approximation to a sine wave whereas at 25% load the averaged current is distorted. This is due to the inability of inductor to follow the reference current at zero crossing due to large value of hysterisis band used in the simulation. The value of inductance used in the simulation was high at 25mH and was intentionally made high to reduce switching frequency. However with a non zero value of inductance some distortion at zero crossing in the current waveform is inevitable .The amount of distortion depends on the value of inductance,value of hysterisis band etc.
This is a fixed switching frequency control strategy. The figure below shows the various components of the control scheme. The negative input of the PWM Comparator is fed with a ramp of magnitude Vs and frequency equal to desired switching frequency. The boost switch is kept on until the ramp voltage equals the error amplifier output voltage Vca.The error amplifier compares the actual inductor current with the reference current represented by a current signal Icp in the figure. The capacitor Cfz will have a value enough to behave as short at switching frequency and hence at switching frequency the amplifier gain will be Rf/R1.This gain has to be limited suitably;otherwise the switching ripple in inductor current getting through the error amplifier can lead to subharmonic oscillations and instability which are well known in the context of current mode control of SMPS circuits. The amplified inductor current downward slope at one input of the PWM comparator must not exceed the oscillator ramp slope at the other input to avoid the instability in the current mode control. This consideration will decide the value of Rf/R1. With this instability removed,the control scheme is essentially a high bandwidth PI controller which can follow the reference current(which contains only low frequency components) very accurately with almost zero tracking error i.e. the average value(averaged over switching periods) of boost inductor current will follow reference current with good accuracy.
The small-signal control to output gain of the boost regulator is (RsxVo)/(VsxsL) where Vo is the output voltage ,Vs is the ramp amplitude,Rs is the current sense resistor and sL is the Laplace impedance of boost inductor. With the known value of Rf/R1 and the above control to output gain , the overall current loop cross over frequency can be estimated and the zero Rf Cfz can be located suitably to obtain about 45 degree phase margin. The function of Cfp is to provide zero gain at very high frequencies to avoid maloperation due to switching noise present the sensed current signal and it does not interfere otherwise with the operation of the control system. This control scheme has the advantages of excellent and fast current tracking and constant switching frequency. The inductor current will have a ripple band superposed on the full wave rectified shape (as in hysterisis control).The amount of ripple can be reduced by increasing the switching frequency or increasing the inductance. The power factor controller IC UC 3854( Price ~ Rs 250/-) manufactured by Unitrode Corporation is designed to implement this average current mode control with the help of few external components. PFC implemented with the help of this IC will result in a THD which is as low as 0.5%.
Fig.10 The Boost PFC Circuit with the complete Voltage Control Loop The voltage control loop of boost type PFC is shown in the figure above. The boost switch,boost diode,current sensing elements,current control loop etc. are absorbed in the block called 'high power factor switching preregulator'.This block accepts the current reference Imo as shown and delivers it as Ichg into the capacitor node. The boost inductor is small in value thanks to the high switching frequency used in practice. The magnetic energy storage and its time variation can therefore be ignored in the power balance analysis. Also as a first approximation, the converter can be taken as loss free. Then the average power delivered to the D.C. side load should be equal to average power taken at the line input. Whatever power is drawn from the line on an instant to instant basis must flow into the capacitor node through the diode if no power is lost in the converter elements and no power is spent in changing the stored energy of the inductor. But instantaneous power drawn from mains has second and higher harmonic content in addition to average content. Hence second and higher harmonic power components flow into output capacitor and result in a predominantly second harmonic ripple across the capacitor. The capacitor size is mainly decided by the ripple that can be tolerated at the output. The output D.C. is sensed and compared with a set reference in the error amplifier. The amplified error is converted into current reference waveform by multiplying it with a waveform template, which represents the desired current wave shape in the boost inductor. This desired shape is that of full wave rectified shape and is readily available at the output of the rectifier bridge. Hence waveform template is taken across the bridge output via Rvac.The analog multiplier output ( usually implemented by transconductance technique) drives the current control loop.(The role of squarer and divider will be explained soon,but if the line voltage is steady the effect of these will be only that of a multiplication constant between multiplier output and current control loop.) The harmonic components of the waveform template which goes into the multiplier consists of D.C., second harmonic and higher even harminics. The output voltage contains second harmonic ripple. If this ripple is passed on to the output of error amplifier and to the multiplier the second and higher harmonic content in the multiplier output get disturbed through cross products. The output ripple does not result in the production of new harmonic components in the multiplier output,but they affect the magnitude and phase of second and higher harmonics present in the multiplier output. It does not look full wave rectified any more. This results in production of third harmonic components in the a.c side current through the modulation process involved in the rectifier bridge. Hence, error amplifier should be dominant pole compensated with a bandwidth much less than 100 Hz.This of course will result in slow loop response. The capacitor across the feedback resistor in the error amplifier effects the required ripple filtering. Assume that the squarer and divider in the figure above were absent and the multiplier output was given directly to the current control loop. The open loop gain from multiplier input (i.e. error amp output point) to the output voltage for small variations at the multiplier input will be decided by the template amplitude i.e. the Vm of line voltage and the capacitor value. Change in multiplier input results in change in line current and power and the capacitor integrates the power change and converts it into change in output voltage. It is basically a first order process dominated by Capacitor-Load Resistance time constant and the gain depends on the value of square of Vm,the line voltage amplitude(change in power µ change in current x Vm).Hence the loop gain and hence the closed loop dynamics will depend directly on square of line voltage and will vary over a range of 1:9 for a PFC with universal input range i.e. 90V-270V.If the closed loop response is adjusted to be critically damped at 90V and full load ,it will be very much underdamped and excessively oscillatory at 270V,no load.Conversely if the dynamics is set for critical damping at 270V,no load condition ,it will be dead slow at 90V,full load condition and will suffer from too high a transient dip in output voltage which lasts too long when load is suddenly applied at output at 90V line condition.It is virtually impossible to maintain satisfactory dynamic performance over a 1:3 line voltage range and 1:10 output load range.This is where the squarer and divider come in. The squarer produces a D.C. output which is proportional to square of Vm.The divider pre-scales the error amplifier output by dividing it by square of Vm.This means that a fixed % change in the error amplifier output always results in the same amount of increase in the power taken from the line,irrespective of line voltage. Or equivalently the open loop gain has been made independent of line voltage amplitude. Now control dynamics changes only due to load change and it is possible make the transient performance satisfactory at least over a 1:3 load range by fixing the error amplifier gain and band width properly. Load throw off is the most severe transient in a PFC.The output voltage rises and this rise is registered only slowly by the feedback system due to its low bandwidth (usually between10 – 20 Hz,has to be low to avoid passing on the capacitor ripple to the a.c side current as explained before) and by the time the control loop acts the output voltage may go to a high level and cause damage to the driven load and/or PFC itself. Also ,due to the unilateral nature of power flow in this kind of PFC,the capacitor voltage will not easily come down having hit the ceiling once-unless there is load or considerable leakage in capacitor. The voltage control loop can do nothing to bring down capacitor voltage under such conditions since power can not flow from D.C. side to a.c side. Additional protection in the form of a fast overvoltage detector resulting in blocking of the switch control signal is needed to clamp over voltage before it goes too high during start-up and load throw-off. The power factor controller IC UC3854 implements the voltage control loop explained in this section fully. The Motorola IC MC 34262 implements the voltage control loop without the squarer and divider part,but incorporates soft start-up and over voltage protection. 5. Power Circuit Design Aspects
Fig.11 Power Circuit of a Boost type PFC System The power circuit components of the PFC are shown in Fig. 11.The resistance Rloss represents the loss resistance of the boost inductor and the two inductors Ls1 and Ls2 represent the wiring inductances.These inductances have a profound impact on the power circuit design and decide the achievable efficiency more or less directly.The switch is usually a MOSFET or IGBT.The diode is an ordinary power diode in the case of PFCs with discontinuous current control and is a fast recovery diode in the case of PFCs with continuous current mode control. The losses in the PFC take place in the form of (i) heating in the current sense resistance (ii) winding and core losses in the inductor (iii) diode conduction and switching losses and (iv) switch conduction and switching losses.The achievable efficiency ranges from 95% to 98% at full load depending upon design and control strategies.Most of the losses (80% to 95% of total losses) take place in the MOSFET/IGBT used as the boost switch.The current control strategy selection has direct impact on the conduction and switching losses in the MOSFET. The switch in the closed condition is an almost linear resistance in the case of MOSFETs and a nonlinear resistance in the case of IGBTs.The MOSFET on-resistance depends strongly on temperature especially in the case of high voltage devices.The on-resistance of the switch results in conduction losses during the time when it conducts current.IGBTs of comparable die size have much lower conduction losses than MOSFETs. During the switching on or off of a switch there is a definite period during which the switch has considerable voltage across it and considerable current through it – i.e. there is a voltage-current overlap period which may last for hundreds of nano seconds to few micro seconds depending upon the switching speed of the device and gate/base drive design.This overlap period is one of considerable dissipation and the average power loss due to this mechanism (called Switching Loss) is directly proportional to the switching frequency and inversely proportional to the switching speed of the device. Assume that the switch was on and it is being turned off.It is possible to turn off a MOSFET at a very rapid rate i.e. the device stops conducting almost abruptly and switching energy will be small.But once the switch stops carrying current the current that was flowing in Ls1 will push into the output capacitance of the MOSFET.This capacitance has a small value.Also,unless this capacitance charges to Vo the diode cannot conduct.Thus the current in boost inductor and Ls1 become energy sources for a highly underdamped circuit comprising Ls1,Ls2,Drain-Source capacitance of MOSFET and diode transition capacitance.The ensuing oscillations result in prominent voltage overshoot across the MOSFET and may lead to device damage.Also these oscillations take place at a very high frequency and contribute to EMI.Thus the price paid for reduced switching loss(by switching off the MOSFET very fast) is in terms of over voltage across it and high EMI (both inside the equipment and outside).Employing an RC snubber across MOSFET will reduce the over voltage ,damp the oscillations and reduce EMI without affecting the turn off switching loss level.But the next time MOSFET goes on it has to discharge the snubber capacitor and this results in increased turn on loss.Also the periodic charging and discharging of snubber capacitor involves CV2f power loss which can be excessive at high frequencies.The value of snubber capacitor depends on the stray inductance level and the worst case load current.Thus the implication of high level of stray inductance during switching off of the MOSFET is either over stress on the device and EMI or reduced efficiency due to snubber loss. Now consider the other switching i.e. diode was conducting and MOSFET is being turned on. A conducting diode has charge storage in it and it remains conducting even after external voltage across it changes polarity till all the charge inside is removed. And the MOSFET is switched on fast in an effort to reduce switching loss. But diode does not let up and hence MOSFET continues to support more or less Vo and the full inductor current is transferred to it at full voltage level. But that is not the end of rise of current in MOSFET.At that instant the diode current becomes zero, but diode continues to be a short since the charge has not gone out of it. Hence the output voltage pumps current in the reverse direction through diode and into the MOSFET.The current through MOSFET rises much above the load current and voltage across it all the while high. This is an extremely high dissipation period for the MOSFET.This situation prevails until all the diode charge flows out under the action of reverse current through it. When all the charge is removed the reverse current in the diode and hence corresponding component in the MOSFET snap and current tends to go to the load current level. But now the two stray inductances, which had been carrying the reverse recovery current component, will resist the current snap action of diode and their magnetic energy storage will cause horrendous ringing of voltage across the just now recovered diode. The diode will fail on over voltage usually. This process of reverse current flow is called reverse recovery of a diode and associated losses taking place in the MOSFET is called reverse recovery losses. The reverse recovery current peak can be up to about 10 to 20 times the rated full load current if the diode is not a fast recovery type. The solutions to the reverse recovery problem are (i) use an ultra fast and soft (i.e. non-snappy) diode (ii) reduce the switching on speed of the MOSFET. Reducing the turn on speed of MOSFET increases the overlap component of switching loss in it and reduces the recovery loss component. Usually an optimum speed can be found out. RC snubber across the diode is almost unavoidable except when it is a super fast recovery diode and stray inductance level is very low. It should be clear from the above discussion that minimising wiring inductances everywhere in the power circuit layout is crucial for reliable and efficient operation of high power PFC circuits. The MOSFET and diode should be mounted on the same heat sink and the drain of MOSFET should be connected to anode of the diode by the shortest link practically possible. Similarly inductance in the source wire of MOSFET should be minimised to preserve the switching speed of the MOSFET.Copper clad plate structure should be employed in the D.C. side to minimise the surge impedance of the D.C. bus. Discontinuous mode current control is easy on the reverse recovery problem since the MOSFET is switched on when the inductor current touches zero. Hence, turn on losses and reverse recovery losses in the MOSFET will be negligible. However, this gain is partially offset by increase in the turn off losses due to higher current levels in discontinuous current control. Also , increased current levels result in higher conduction losses in these schemes. Continuos current control schemes have to handle the reverse recovery problem by selection of an ultra fast recovery diode and requires careful circuit layout. However switching ripple is at a low level in these schemes and hence ripple filtering is easy. Current stresses in the active devices also is less.
Fig.13 Current waveforms at full load for the 1kW design The Fig. 12 shows the circuit diagram of a single phase PFC using average current mode control and rated for 1kW.It can accept input voltages in the range 150-230V.It has an efficiency of 93.8% at full load and the MOSFET losses under that condition is 50 W and is high due to slow switching. The Fig.13 shows the simulated boost
inductor current and line current waveforms for full load at 230V line.
The switching frequency is 50kHz.
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