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Introduction

Synchronous Link in Active Power Quality Conditioners (APQC)

A Single Phase APQC without Battery Backup

Basic principle of Power Quality Conditioner

Control of Power Quality Conditioner

Simulation Model Of The Scheme

Analysis Of Waveforms Obtained From Simulation 
 

[ This article was prepared for a short-term course offered by Department of Electrical Engg.,NIT Calicut in 2000]

1.  Introduction

Deterioration of Power Quality due to the connection of a large number of non-linear loads in the power system network has become a major concern world over in the recent years. Whenever a large load is switched into or switched off from the network, a sag or swell of the supply voltage for 2 to 5 cycles is very common. Also, a sustained dip or rise in voltage level around 230V is common. To protect the voltage sensitive devices from this kind of hazards, a voltage stabilizer is required which will not let the variation in supply voltage to affect the device by keeping the voltage across the device fixed.

The other way to look at the use of power quality conditioner is that due to increasing use of electronic devices, the quality of power is getting corrupted. This is because harmonics are injected into the supply by the electronic/industrial electronic loads which are mostly non-linear in nature.

A single phase PWM Inverter based Active Power Quality Conditioner (APQC, sometimes called Active Power Line Conditioner too) which can deliver clean, stable and regulated AC voltage to a critical load working from an AC line which suffers from poor power quality including sags, swells, transients and harmonics is discussed in this article. This device takes care of the sags, swells as well as sustained voltage dip/rise in the supply. It also takes care of the power quality of the system by preventing the harmonics produced by the loads being injected into the supply and isolates the load from voltage harmonics that may be present in the line.

2.  Synchronous Link in Active Power Quality Conditioners (APQC)

Basic Principle Of a Synchronous Link

Fig. 2.1 Synchronous Link

A PQC is essentially a synchronous link. Various topologies differ only in control strategies. Consider two synchronous AC sources connected through a reactor i.e., a synchronous link. 
Assuming the reactor to be lossless, the active and reactive power equations can be found out as follows: 

1. Real power flow P takes place from the leading bus to the lagging bus. It is proportional to sin a and it does not depend much on the voltage difference |V₁ – V₂|.
2. Reactive power flow takes place from the bus with higher voltage to the bus with lower voltage. It is proportional to |V₁ – V₂| and does not depend much on the relative phase angle .

Fig. 2.2 Block diagram of the APQC

The link reactor serves another purpose also. When any harmonic current is required for the load, most part of it comes from the inverter side because the link reactor presents high impedance to harmonics. The supply current remains essentially sinusoidal even for non-linear loads.

In steady state, when the supply is present, the inverter supplies only reactive power. However, during the transient period (i.e., when load is switched on), the active power must also come from the inverter. If the PQC is without backup, this drawing of active power will result in an appreciable dip in the capacitor voltage that should be corrected immediately by drawing more active power from the source. So, the control of the PQC without backup should be very fast.

But if the PQC  has a backup source, the DC side voltage will not dip even if the active power is taken from the inverter. This eases the control strategy. Even if the control is a bit slow, the buffering action of the battery will prevent uncontrolled transients in the system.

The PQC without backup source can function only when the supply is present because it needs to draw active power from the supply to maintain its DC side voltage. But the PQC with backup source can function even when the mains supply is absent. 

3.  A Single Phase APQC without Battery Backup

3.1  Basic principle of Power Quality Conditioner

The Active Power Quality Conditioner is expected to provide a constant amplitude sinusoidal voltage to the load against a varying line input; all the while drawing a sinusoidal current even when the load is non-linear. The principle of synchronous link power flow is used in the system.

Active power flows from leading bus to lagging bus in a synchronous link and it is proportional to lead angle (in radians) for small variations of current. Reactive power flows from higher voltage magnitude bus to lower voltage magnitude bus and is roughly proportional to difference in voltage magnitudes. 

 In the APQC without Battery backup, one of the two AC sources is the AC mains voltage whereas the other one is the output of the PWM sine wave inverter running from a DC voltage assumed to be available from a charged DC side capacitor. A link inductance L links them up and the load is connected across inverter output. 

If the inverter is a loss-free one, the active power flow from the line into the inverter will get translated as an even increasing voltage in the DC side capacitor. Similarly, an active power flow out of the inverter will eventually take the DC side to zero voltage condition. It is necessary that the DC side capacitor voltage be maintained at a fixed value (at least within a band around the nominal value) in order to synthesize a rated amplitude sinusoidal output at the inverter for all load conditions. Practical constraints on the maximum modulation index achievable in a Sinusoidal pulse Width Modulated (SPWM) inverter will put the desired DC bus voltage in the range of 350 V to 370 V DC. Thus, in a loss-free inverter, the active power flow from the line must be exactly equal to the active power required by the load and no active power must flow into or out of the inverter under steady state and the inverter must be able to draw/deliver active power when the DC side capacitor voltage is to be corrected. This calls for a continuous adjustment of phase angle of inverter output conditioned upon the value of the DC side capacitor. 

Usually the switches in the inverter will have diodes connected across them. At the time of startup, the DC side capacitor will charge up to the line voltage peak through the line inductor and these diodes like in any ordinary rectifier circuit. After that the active power flow control will maintain the DC side voltage at the desired value. If the inverter has losses, the active power flow control will maintain the power flow into the inverter at the right value such that the losses are met and there is no extra power left to upset the capacitor voltage. 

A non-linear load draws a non-sinusoidal current. This current can come from two paths – from inverter and from line. The active fundamental component will come from line side as per the above logic. The reactive component may come from line or inverter or both depending upon the line voltage conditions. And the harmonic components of the load current will come from both line and inverter. If the inverter output impedance had been zero all the harmonic currents would have come from the inverter and hence line current would have been a pure sine wave. But the inverter output impedance will not be zero; hence part of the harmonic current flows in the mains line too and this will result in line current distortion as well as output voltage distortion. However, inverter impedance is small compared to link impedance and hence only a very small portion of total harmonic current generated by the load will flow through the line. It is possible to bring down the distortion in both the line current and output voltage to less than 5% by proper control of inverter output filter impedance. 

3.2 Control of PQC

Essentially three types of control strategies are applicable to a PQC.

The first is the phase angle control scheme. Here the controlled variable is DC side capacitor voltage and the variable used for control is phase lag of inverter output with respect to line. A synchronous but phase shifted sine wave is synthesized from line and given as the reference input for inverter. Inverter is gated as per sinusoidal PWM logic or delta modulating logic to produce a constant amplitude sine wave output. The phase of this output is controlled in such a way that DC side voltage is maintained constant. A PI control system is used for this purpose and a voltage to phase angle converter implements the control finally. A secondary control loop that senses the amplitude of inverter output and adjusts the amplitude against load variations may be needed if tight control of regulation is required. But if regulation within ± 5% is sufficient, such a loop can be dispensed with. The most important disadvantage of this control scheme is its slow response and prominent overshoots and undershoots in the DC side voltage and corresponding swells and sags in line current during transient conditions.

The second control strategy is direct current control of inverter i.e. it converts the voltage source inverter into a current regulated PWM inverter. Two sinusoidal templates – one sinusoidal and in phase with a.c. line and second sinusoidal and 90⁰ leading w.r.t a.c. line i.e cosine – are generated from the a.c. line using a PLL based system. DC side voltage is sensed and compared with a set reference value. The resultant error is used to amplitude modulate the sine wave template and the result will be the desired active component of current that the inverter has to draw from the line. Similarly, the inverter output voltage amplitude is sensed and compared with a set reference value. The resultant error is used to amplitude modulate the cosine template. The result is the desired reactive current that the inverter has to draw. These two current references are added to form the reference current for the inverter. The actual current in the inverter is fed back into a current control loop and the inverter switches are gated in order to bridge the gap between the reference and the actual current by hysteresis control or unipolar switching scheme. 

Considerable improvement in speed and accuracy results in this control scheme. However, the current control loop can be difficult to compensate due to sharp changes in phase lag of inverter filter at about its resonance frequency. Also this kind of feedback current control tends to be sensitive to noise pickup in the current sensing process. 

An indirect current control is used in the third control scheme. Assume that all impedances between the AC line and DC side capacitor are precisely known. These include link inductance value, its resistance, inverter filter impedance and inverter equivalent resistance. The reference current i.e., the current that the inverter must draw in order to maintain the DC side voltage and output voltage constant is calculated in the same way as in the case of the second control scheme described above. If all impedances are known and the line side voltage is known, the inverter internal output voltage required to make this current flow in the link can be calculated by adding the impedance drop to the line voltage. This calculation is done in real time in analog OpAmp circuits and the inverter voltage reference is created thereby. If all impedances are accurately known, the actual current will be equal to the reference current. However, due to error in parameter measurement/estimation, a current feedback loop will be needed in practice in this scheme too. But this feedback loop needs to have only a small gain and need not be compensated at all. Also, if PI control is employed on capacitor voltage and output voltage, this minor current loop can be removed. Even if only proportional control is used everywhere, the allowed tolerances in regulation will make the current feedback unnecessary. Similarly, if link impedance is the dominant impedance, other impedances may be ignored in calculation at the expense of slight degradation of output voltage regulation. This is the control scheme that is considered further in the sections that follow.

With the fundamental component of current flow in the AC side of the inverter, the DC side capacitor will have second harmonic current flow and resulting second harmonic ripple in the voltage across it. Size of this capacitor is selected to reduce this ripple. But when this capacitor voltage is sensed and compared with a set value, considerable filtering will be needed to avoid injection of third harmonic into the active current reference. Such filtering makes a system sluggish and gain/phase margins also come down resulting in impermissible overshoots and undershoots in the capacitor voltage. Hence, a sampling scheme with sampling period of 10ms is generally used to derive the capacitor voltage signal needed for control purpose. A similar sampling scheme senses the AC source voltage at peak and avoids filtering in that sensing path too. These two sampling processes make it possible to implement corrections in one half cycle, thereby permitting the use of a lower value of capacitor than what would have been necessary otherwise. Further, the control scheme compensation is simpler with this sampling scheme.

Indirect Current Control Based APQC Control

From the block diagram (Fig. 3.2), it can be seen that, Inverter output voltage = AC supply voltage + Inductor drop =  where, "i" consists of active and reactive components.

To realize this, the supply voltage is peak sampled and compared with 230V reference. This error is multiplied by the cosine template to give the reactive current reference. Likewise, the capacitor voltage is sampled and compared with 350V reference. This error is multiplied by sine template through an analog multiplier to give the active current reference. Adding these two currents, the current reference is obtained. This current is differentiated with a gain of L so that L( di/dt) is obtained. This is added to the supply voltage to get the output voltage.

In this scheme, there arises the need for DC offset control. The input AC source will not contain any DC component but the synthesized AC provided by the inverter may contain DC. This may be due to the fact that the switches are not identical and switching times are not similar. This DC will appear as a 50 Hz current on the capacitor side. This 50 Hz current should ideally create a cosine ripple in the capacitor voltage that will give only a second harmonic in the inverter output. But because of the non linear relationship between voltage and energy ( E = ½ CV² ), an upper excursion of voltage of voltage ripple will be of lower magnitude than the lower excursion. This will result in a 50 Hz sine content in capacitor voltage. The fundamental cosine content in capacitor voltage results in pure second harmonic in the output. But fundamental sine content in capacitor voltage results in further generation of DC content at the inverter output which will eventually be limited only by the total resistance present on the AC side. The DC current can be eliminated by giving a DC offset to the inverter control voltage. The offset given is controlled by the magnitude of the DC current present in the AC side. A low pass filter on the sensed inverter current measures this magnitude.

The inverter control voltage is obtained by adding this offset control voltage to the inverter output voltage. This control voltage is compared with the high frequency triangular wave to be used in SPWM scheme to provide gating signal to the MOSFETs/IGBTs.

3.3  Simulation Model Of The Scheme

3.3.1 Simulation of Control Dynamics

(a) Reactive Current Control Block

This hierarchical block is used to obtain the reactive current reference from the supply voltage. In this block, the scaled down supply voltage is peak sampled using a transistor that is switched at 10ms intervals by a square wave generator (VPULSE) of 10us pulse width. This signal is held by a capacitor, inverted and added with a 1V-amplitude reference voltage (which represents the 230V supply). The error is multiplied by the inductor impedance using an E-device. This is passed through a limiter and multiplied with the cosine template. The output of the multiplier is the required reactive current reference.

(b) Active Current Control Block

This hierarchical block is used to obtain the active current reference from the scaled down DC capacitor voltage. The conversion scheme followed is same as in the previous case. However, the reference voltage is 1.0937V (representing 350V DC). Also, after the limiter, the error signal is multiplied with the sine template. The resultant signal is the active current reference.

(c) Inverter Control Voltage Block

This hierarchical block is used to obtain the inverter modulation voltage from the active and reactive current references and the supply voltage. Here, the current references are added together and differentiated in a differentiator. This is added to the scaled down supply voltage and passed through a limiter. The output obtained is the inverter modulation voltage.

(d) PWM-Converter Model

This hierarchical block is used to calculate the output voltage of the inverter after filtering as well as the capacitor current. The DC offset control is also calculated in this block and is added to the inverter control voltage. The top ABM block is used to calculate the inverter output voltage. Here, the inverter control voltage is multiplied with the DC capacitor voltage (referred to a 320V scale). The output is the required voltage. The bottom ABM block is used to calculate the DC side capacitor current. In this, the inverter output voltage (obtained from the first ABM block) is multiplied with the inverter output current (obtained from the H-device) and this is divided with the capacitor voltage. The resulting current is the capacitor current. The implied principle is one of instantaneous power balance between DC side power and output side power in the inverter, neglecting the losses in the inverter and changes in energy storage in the inverter output filter components. 

(e) Load

A non-linear load consisting of a rectifier and an R-L load connected in parallel is contained in this hierarchical block. Either the R-L load or the rectifier load was made active at various instants for different simulation runs using switch models available in PSpice.

(f) Perturbation AC

The perturbations in the supply are introduced by multiplying two voltage sources (VSIN) and adding this to the original source voltage. Such an arrangement can produce different source disturbances including an amplitude-modulated wave.

3.4  Analysis Of Waveforms Obtained From Simulation 

A PQC based on the above models was simulated using Microsim Pspice (Design Lab 8.0) package. The results of simulation studies are included in the sections that follow. The system simulated had the following parameters.

Rating - 500VA, Input –Single Phase 170 t0 270 V, Output – 230 ± 5% V

Inverter Loss Resistance – 3 ohms , Inverter Output Filter Inductance – 4mH 

Output Filter Capacitances – 1uF in parallel with series combination of 1uF & 100 ohms

Link Inductor – 96mH with 2 ohms resistance

Inverter Details – Single Phase Full Bridge MOSFET Inverter using IRFP450 MOSFETs

Inverter Modulation Scheme – Unipolar Sinusoidal Modulation at 20kHz
 

3.4.1 Simulation of control dynamics for various load conditions

Case 1 : Rms. line voltage 230V with 500VA R-L load of 0.6 p.f switched on at 100 ms

Figure 3.4.1 show the source voltage, output voltage, source current, load current, inverter current and capacitor voltage. Before the load is switched on, a very small source current is drawn in order to supply the inverter losses. The load gets switched on immediately after the sampling of the capacitor voltage has been done. So for the next 10ms, the active current reference cannot change. The capacitor has to supply the power during this time. This explains the dip in capacitor voltage at 100ms. At 110ms, the capacitor voltage is sampled and the active current reference changes accordingly. This change in active current reference causes phase shift in the inverter output voltage resulting in current flowing through the link inductor. 

At the time of sensing (110ms), the capacitor voltage was at the lowest point. So active current reference is made somewhat larger resulting in a high source current than required. The next cycle of load current will be then somewhat lower. These oscillations in source current and capacitor voltage will be damped out in a few cycles. 

The capacitor voltage has a 100 Hz ripple that occurs because of the 100 Hz ripple in the power on the AC side. A steady state error in the capacitor voltage can also be seen. This happens because only proportional control has been used.

In steady state, the inverter is supplying all the reactive power. This is evident from the fact that the inverter output voltage and output current are at a phase shift of 90 degrees.

Case 2 : Rms line voltage changes from 230 V to 170 V at 200ms with R-L load switched on at 40ms.

Figure 3.4.2 shows the source voltage, output voltage, source current, load current and inverter current. The waveforms similar behaviour as in the previous case when the load is switched on. Source voltage decreases to 170V at 200ms. But this dip in source voltage is not recognized instantaneously by the reactive current reference block because the next sampling of source voltage will take place only at 205ms. So the reactive current will continue to be the same resulting in the inverter output voltage following the source. At 205ms, the reactive current reference will change which results in a sudden rise in the inverter output voltage. This sudden rise will appear as a step input to the LC filter resulting in some oscillations in the output.

The link inductor current will change at 205ms reflecting the change in the reactive current reference. 

The inverter output current, after 205ms, shows that the inverter is supplying both the lagging reactive power needed by the load and the lagging reactive power required for making the output voltage constant. For power balance, as voltage decreases, the inverter and link current increase.

Case 3 : Rms line voltage changes from 230V to 270V at 200ms with R-L load switched on at 40ms.

Figure 3.4.3 shows the source voltage, output voltage, source current, load current and inverter current. This is similar to the previous case except in the inverter current after 205ms. The leading reactive power requirement for making the output voltage constant cancels out the lagging reactive power requirement of the load. Hence the inverter output current is almost zero. 

The source current after 205ms is leading the inverter output voltage keeping the output voltage at 230V.

Case 4 : Rms line voltage = 230V with 300W rectifier load switched on at 40ms.

Figure 3.4.4 shows the output voltage, link current, the load current and the inverter current. The waveforms are shown from 100ms to 160ms. Output voltage shows clipping at its peak because at this moment, the diodes conduct and the output voltage is the same as the capacitor voltage which cannot change instantaneously. Small filter oscillations can be observed in the output waveform when the diodes of the rectifier stop conducting. For damping the oscillations, a coupling capacitor with a resistor is used.

The input current waveform remains appreciably sinusoidal even with the load current being of pulse nature. The THD of the input current was calculated and it was found to be well within the accepted limit of 5%. See Table 1

The inverter supplies both the reactive power and the current harmonics. This is manifested in the output current waveform of the inverter. The small oscillations seen are filter oscillations.

Case 5 : Rms line voltage changes from 230V to 170V at 200ms with rectifier load switched on at 40ms.

Figure 3.4.5 shows source voltage, output voltage, link current, load current and inverter current. After 40ms, the output voltage shows some clipping at the peak which was already explained. When the line voltage changes at 200ms, the corresponding adjustment in the output voltage takes place only at 205ms as was previously explained.

Till 40ms, the inverter output current was almost zero. From 40ms to 50ms, the inverter supplies the active power to the load. From 50ms to 205ms the inverter supplies the harmonic current as well as the reactive power required by the load. From 205ms onwards, the decrease in the source voltage causes the inverter to supply the extra reactive power required to make the output voltage 230V.This explains the inverter current waveform.

The source current waveform remains more or less sinusoidal in this case also. The THD has been calculated and was found to be less than 5% (Table 2). The capacitor voltage waveform shows the fact that the reactive and harmonic currents are supplied from the inverter. 

Case 6 : Rms line voltage changes from 230V to 270V at 200ms with rectifier load switched on at 40ms.

Figure 3.4.6 shows the source voltage, output voltage, and link current, load current and the inverter current. Up to 200ms, the waveforms are similar to those in case 5. After 200ms, the inverter will supply leading reactive power in order to make the output voltage 230V. This explains the source current and inverter current waveforms. An expanded view of the above waveforms after the change in voltage is shown in Figure 3.4.6 (Details).

Case 7 : Rms line voltage changes from 170Vto 270V continuously (Amplitude Modulated wave) with R-L load.

Figure 3.4.7 shows the source voltage, output voltage and link current. Link current is lagging when source voltage is high and leading when the source voltage is low.

One interesting observation is made here. The maximum value of the inverter output voltage occurs when the supply voltage is minimum. Similarly, the minimum value of the inverter output voltage occurs when the source voltage is maximum. In other words, the system is over-compensated. This over-compensation comes from the DC offset control mechanism. The low pass filter used to extract the DC current will pass some amount of the 50 Hz component also (around 2%). This will result in the inverter control voltage being somewhat over-compensated. 

Download the Microsim Design lab 8.0 Schematic Files