DspEdu 2.1

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1. Introduction

2.  A Multi-Functional UPS Using a Phase-Controlled High Frequency Isolated DC-AC Converter

2.1 Phase-Controlled High Frequency Isolated DC-AC Converter

2.2 Snubber Requirements and Efficiency Considerations

2.3 Multi-Functional UPS

3.  High Frequency Isolated On-Line UPS Topologies
 
 

[ This article was prepared for a 3-day short-term course I offered to working professionals from UPS Industry in 1998-2001 period.]

1.  Introduction

The battery voltage level used in most of the small and medium power rated UPS will be of low value compared to the d.c voltage required to synthesize sine wave output of 230V r.m.s value by SPWM without using a level shifting transformer. The battery level is 12-24V up to 1kVA rating, in the 36-48V rating up to 3kVA and 120V for rating up to 10kVA.It is true that many manufacturers have started employing 360V battery even in the rating range of 500VA to 10kVA.But there are definite advantages in using as low a battery voltage as the current power semiconductor technology permits from the point of view of battery life and better reliability from UPS.

The mismatch between the d.c bus level and the peak value of a.c output needed – 320V or so- necessitates the use of a 50Hz transformer between the inverter output and the final UPS output. This transformer adds to the weight, size, cost and losses of the UPS. Isolation between the input line as well as battery and UPS output is needed in a UPS and this is another reason why a 50Hz transformer is needed almost always.

Many new high frequency switching topologies which use high frequency ferrite transformer isolation for level shifting and galvanic isolation have been proposed in the recent past and many of them have been turned in to commercially viable UPSs. However one major problem stands in the way of this high frequency isolated units. A bypass to mains (synchronized or unsynchronized) is invariably needed in most medium and high power UPS units. This bypass may be used to transfer the load to mains when inverter detects fault on self diagnosis or when inverter fails or when UPS is taken down for repair or maintenance. Static switches or electromechanical contacts can do this transfer. If static transfer is used it becomes impossible to galvanically isolate the UPS output if the UPS is of high frequency isolation type. An extra 50Hz transformer rated for full output rating of UPS will have to be interposed between the UPS output and the load to achieve galvanic isolation in that case. If the transfer to bypass is by contactors/relays galvanic isolation is preserved even in high frequency isolation based UPS when the load is on UPS. But once the load is transferred to bypass the load will not have galvanic isolation from the mains. But this is usually acceptable since it is expected that the supply integrity of the supply given to load in the bypass mode of any UPS is suspect and the load is not expected to be left on bypass for extended periods.

Thus one can think of high frequency isolation UPS designs when the bypass to mains is done by electromechanical means and galvanic isolation is not needed when the load is on bypass. Some popular high frequency topologies for UPS design are discussed briefly in this article.

2.  A Multi-Functional UPS Using a Phase-Controlled High Frequency Isolated DC-AC Converter

2.1 Phase-Controlled High Frequency Isolated DC-AC Converter
 

This converter makes it possible to convert a d.c voltage in to a.c output with level translation and galvanic isolation using high a frequency transformer. The converter is bilateral i.e., active power can flow from d.c side to a.c side or from a.c side to d.c side. This makes it possible to use the same converter to charge the battery from a.c mains when the a.c mains is present and healthy and to deliver a.c output to the load when the mains fail. A typical inverter of this type is shown in the Figure.1.

It takes two stages of conversion to produce a.c from d.c in this converter. The first stage conversion takes place in the push-pull stage in Fig.1.(This could very well be a full bridge or half bridge stage instead of push-pull as shown depending on battery voltage and the power to be handled in the converter.)This stage is gated using 50% duty ratio waveforms at the gate. The voltage across L1 and L2 will be square waves of amplitude equal to battery voltage and duty ratio equal to 50% and will be 180-degree phase shifted with respect to each other. The waveforms across L3 and L4 will be similar but the amplitude will be scaled by a factor ‘n’ equal to the turns ratio of half windings. The second stage conversion is done by the bilateral switches M3 and M4.When M3 is ON the voltage across L3 is connected to the filter and when M4 is ON the voltage across L4 is connected to filter irrespective of the polarity of the voltage thus connected (because the switches M3 and M4 are bilateral). These two switches are also gated by 50% duty ratio square gate waveforms (of course with proper isolation); but these gate waves as a group is shifted in phase by j with respect to the gate wave group of the first stage. This is shown clearly in Fig.2.Also, the waveform of voltage that appears across the filter input is shown in the same Figure. This will be a bipolar waveform of ± nV with positive half cycle and negative half cycle durations related in the ratio (p -j ):j and will have a frequency which is double that of the switching frequency of the first stage. The L-C filter at the output filters out the high frequency content in the output and the output wave will be a d.c of value = nV x (1-2j /p ). The output will be nV when j = 0 , it will be 0 when j = p /2 and it will be –nV when j = p . Thus by controlling the gate signal phase shift between -p /2 to +p /2 it is possible to control the output from –nV to +nV through zero. The converter is bilateral since the first stage is a familiar bilateral bridge and the second stage contains only bilateral switches that can withstand voltages of both polarities and conduct currents in either direction.

Simple analog or pulse electronics can be used to synthesize the required gate waveforms and being 50% duty ratio waveforms they can conducted across isolation barrier by means of pulse transformers. The phase shift between the gate waveforms of the first and second bridges will be made proportional to a low level sinusoidal reference signal of 50Hz.The converter will synthesize a a.c wave of amplitude equal to nV if the phase shift modulation is of full depth. The wave shape at the output will be same as that of reference wave if all the drops in the inverter and filter can be neglected. But, in practice due to non-linear drops and filter dynamics the wave shapes may differ slightly and instantaneous feedback based closed loop control may be needed for close waveform control.

The control strategy and application decide the direction of power flow in this converter. For e.g. if the d.c side is a battery and a.c side is terminated in a load the power will flow from battery to load and the controlled variable will be the output voltage waveshape and amplitude. If the d.c side is terminated in a capacitor and a.c side is connected to an a.c source power will flow from a.c side to d.c capacitor and control of converter will be aimed at maintaining the d.c side capacitor voltage constant by adjusting the real power d3rawn by the converter from the a.c source. Both synchronous link phase control or current regulated operation can be used to achieve this. In this application the converter becomes a switched mode rectifier. If the d.c side is a battery and a.c side is connected to an a.c source the real power can be made to flow from a.c to battery thereby making the converter a battery charger.

2.2 Snubber Requirements and Efficiency Considerations

The major problem (which restricts its range of application severely) with this converter is its excessive Snubber requirements and consequent reduction in efficiency at higher power levels.

MOSFETs and IGBTs take time to switch ON and OFF. Hence the incoming switch has to be delayed a bit i.e. the gate for the switch which is to go ON should released only after a delay after the one which is to go OFF had been given the command. This is necessary to avoid the cross conduction problem. During this delay period all switches of a bridge will be OFF and current flow (which can not be broken due to inductances) takes place through the companion diodes of MOSFETs or intentionally connected diodes of an IGBT bridge usually. But this kind of a path will not be available in the case of a bilateral switch since there can not be a diode shunting a bilateral switch.

Thus, when both M3 and M4 are OFF during the delay between the conduction changeover between them there is no path for the current to. The current can not be broken due to transformer leakage inductance and filter inductance. The energy stored in these inductances will rapidly charge/discharge the device capacitances of the switches and cause excessive voltage overshoots across the devices thereby damaging them. Therefore the devices will have to have protective R-C snubbers across them. But employing snubbers across the switches will only result in shifting the location of energy loss i.e., the energy stored in the inductances will be lost in the snubber resistances and additional losses due to charging and discharging of snubber capacitors also add to the losses. Of course application of snubbers will solve the voltage overshoot problem and will protect the devices; but at the expense of efficiency. The circuit in Fig.1 shows a protection circuit in the form of an overvoltage clamp snubber.

Increased switching speed will result in lower snubbing requirements and will result in lesser energy loss. But there are limits to it. As the output current increases the snubbing energy also increase. This loss of energy limits the application range of this converter to ratings below 1kVA.

2.3 Multi-Functional UPS

This multi-functional UPS topology was already discussed in another lecture. A delta modulated 50 Hz transformer based inverter was used there to explain the principle of operation. Here the high frequency isolated DC-AC converter is used in its place.

A sine wave reference of fixed amplitude and line frequency is generated in control electronics and it stands to represent the fixed amplitude output voltage required across the load. Phase Locked Loop that gets the stepped down version of a.c line voltage obtains this reference wave. The battery charging current is sensed and is compared with a set reference value. The error signal is sent to a PI controller. The PI controller output produces a phase shifted version of the reference sine wave, the phase shift being proportional to the PI controller output. Controlling the phase shift between the voltages at the two ends of the link inductor controls the active power flow and thereby controls the charging current in to the battery. The output voltage amplitude is sensed and compared with 230V reference. The error is made use of to adjust the amplitude of phase shifted reference sine wave in order to maintain the output amplitude constant.

When the a.c mains fail the phase angle control system which tries to maintain the battery charging current constant will saturate and the system will keep producing the same old amplitude at the output by virtue of the free running property of PLL. Thus the transfer to battery is breakless. Also the link inductor provides a great degree of isolation of the load from mains as far as mains transients are concerned. Of course it is not a galvanic isolation. (See the lecture notes on Active Power Line Conditioners for more details on multi-functional UPS). It is also possible to make this UPS draw only unity power factor current from the mains by suitable modifications in the control strategy. But in that case the load voltage amplitude can not be maintained constant and will follow variations in supply voltage magnitude.

3.  High Frequency Isolated On-Line UPS Topologies

The UPS described in the last section provides the load with a constant amplitude sine wave output without any break. But there is no true galvanic isolation between the load and the a.c mains. While it is true that the link inductor attenuates the line transients, surges etc to a large extent it is still possible that the load is subjected to large magnitude impulses from the line. Hence this UPS output will need a well-planned and coordinated surge protection across its terminals. True galvanic isolation is possible only in an on-line structure. Two popular on-line structures are described further in this section.

Fig.4 shows a UPS structure which draws power from mains (single or three phase) at unity power factor and sinusoidal waveshape and uses a separate battery charger.

The PFC circuit at the front end draws sinusoidal current at u.p.f and maintains the voltage across the output capacitor Cb at a constant value –usually at 400V.An isolated phase controlled DC-AC Converter described in section2 of this lecture runs continuously from this high voltage d.c bus providing a fixed amplitude sinusoidal output to the critical load. This converter has a dedicated voltage control loop which controls its output voltage against variations in d.c voltage and output load. The filter components Lf1(a small valued ferrite core inductor) and Cf1 (small valued a.c capacitor ) isolates the d.c bus (the capacitor Cb) from the high frequency switched mode current components drawn by the DC-AC converter. The PFC part is usually run at 50-100kHz switching frequency and the DC-AC converter at around 20kHz.

A high frequency isolated half bridge or full bridge using a ferrite core transformer interfaces the low voltage battery to the 400V d.c bus for charging. The filter components Lf2 and Cf2 isolate the battery from high frequency swithed mode currents of SMPS. This SMPS is duty ratio controlled using current mode control and maintains the battery charging current at the set value by closed loop control. When the battery is depleted the set value will be the so called bulk charging current and is usually 20% of its AH rating. As the battery picks up charge its voltage rises and the battery voltage is continually monitored. When the battery voltage reaches the over-charge value an outer voltage control loop comes into action and changes the setting for charging current such that the battery voltage is maintained at the over-charge voltage. This outer loop changes the current setting for the SMPS and SMPS continues to function in the current controlled mode. In this over charge mode the battery charging current tapers down with time and when it has come down to about 30% of bulk charge current value the charger enters the float mode. In this mode the outer voltage control loop maintains the battery voltage at the float voltage value by suitably adjusting the current reference for the current controlled SMPS. This battery-charging algorithm was covered in detail in the lecture on Battery Management earlier in this course. For a 48V battery the usual setting for over-charge voltage is 56V and the float voltage is 53.5V.Thje low battery shut down is usually set at 44V.Thus the battery voltage has a range of 44-56V in a UPS using 48V battery.

A DC-DC Boost converter with high frequency ferrite transformer isolation interfaces the battery bus to the high voltage d.c bus for feeding the DC-AC converter when the mains power fails. This could be a half bridge or full bridge SMPS and is gated at 50% duty ratio with no duty ratio control. The filter components Lf3 (a small ferrite core inductor) and Cf3 (a large electrolytic capacitor) do high frequency filtering. The switching frequency of this converter is usually between 50-100kHz. The transformer turns ratio is chosen in such a way that the output voltage of this boost stage is always below the d.c bus voltage (400V) maintained by the PFC stage. Thus when the mains is present and healthy the PFC will maintain the d.c bus at 400V and the boost SMPS will be a sort of back biased and will function without any current flow. All the load power and battery charging power will be delivered by PFC stage. 

PFC will draw higher currents at lower input voltages for the same power output. When the input voltage comes down to low values the control system of PFC will saturate and the PFC will function drawing a constant amplitude current and will not attempt to maintain the output voltage any longer. When this happens the d.c bus voltage comes down and when it comes down to a level equal to the output level of the DC-DC Boost SMPS this SMPS starts delivering current to the d.c bus and thereby takes over the task of supplying power to the inverter. There is no change over and the transfer to battery is smooth. In fact both PFC and the battery will feed power to the d.c bus node for low a.c line conditions till the line voltage goes so low as to cause a PFC shut down. But once the Boost converter starts feeding current into the d.c bus the battery charger SMPS should be inhibited. This could be done by a control signal based on the current drawn by the boost converter from the battery.

The major disadvantage of this topology is that it requires an isolated DC-AC converter. It has been pointed out that the phase controlled DC-AC converter is limited in its rating to about 1kVA usually due to excessive snubber losses. May be it could be stretched to 2kVA; but not more.

Mains isolation is built into the PFC stage itself. Isolated Flyback PFC is easy to design at low ratings say up to about 600W but tends to somewhat inefficient at higher power levels. Isolated boost single phase PFC can take one to about 3kW and to 6kW if interleaved units are used. A three phase unit can easily have 10kW capacity.

The boost converter is driven at 50% duty ratio without any PWM control. Sinusoidal Pulse Width Modulation with closed loop voltage amplitude control is used at the inverter stage for exercising control on the output. Lf1, Lf2, Lf3 are ferrite core inductors of small value. Cb is a bulk capacitor and the other capacitors are high frequency filter capacitors of small value.